Freescale Semiconductor, Inc.
Timing System
Computer operating properly watchdog function
8.6.3 PACTL — Pulse accumulator control register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Pulse accumulator control
$0026
0
PAEN PAMODPEDGE
0
I4/O5 RTR1 RTR0 0000 0000
(PACTL)
Bits RTR[1:0] of this register select the rate for the RTI system. The
remaining bits control the pulse accumulator and IC4/OC5 functions.
Bits 7, 3 — Not implemented; always read zero
PAEN — Pulse accumulator system enable (refer to Pulse
accumulator)
PAMOD — Pulse accumulator mode (refer to Pulse accumulator)
PEDGE — Pulse accumulator edge control (refer to Pulse
accumulator)
I4/O5 — Input capture 4/output compare (refer to Pulse
accumulator)
RTR[1:0] — RTI interrupt rate select
These two bits determine the rate at which the RTI system requests
interrupts. The RTI system is driven by an E/213 clock rate that is
compensated so it is independent of the timer prescaler. These two
control bits select an additional division factor. Refer to Table 8-2.
8.7 Computer operating properly watchdog function
The clocking chain for the COP function, tapped off from the main timer
divider chain, is only superficially related to the main timer system. The
CR[1:0] bits in the OPTION register and the NOCOP bit in the CONFIG
register determine the status of the COP function. One additional
register, COPRST, is used to arm and clear the COP watchdog reset
system. Refer to Resets and Interrupts for a more detailed discussion
of the COP function.
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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