Freescale Semiconductor, Inc.
Timing System
Input capture
8.4.1 TCTL2 — Timer control register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
bit 0
Timer control 2 (TCTL2)
$0021 EDG4BEDG4AEDG1BEDG1AEDG2BEDG2AEDG3BEDG3A0000 0000
Use the control bits of this register to program input capture functions to
detect a particular edge polarity on the corresponding timer input pin.
Each of the input capture functions can be independently configured to
detect rising edges only, falling edges only, any edge (rising or falling),
or to disable the input capture function. The input capture functions
operate independently of each other and can capture the same TCNT
value if the input edges are detected within the same timer count cycle.
EDGxB and EDGxA — Input capture edge control
EDGxB EDGxA
Configuration
ICx disabled
0
0
1
1
0
1
0
1
ICx captures on rising edges only
ICx captures on falling edges only
ICx captures on any edge
There are four pairs of these bits. Each pair is cleared by reset and
must be encoded to configure the corresponding input capture edge
detector circuit. IC4 functions only if the I4/O5 bit in the PACTL
register is set.
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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