Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Alternate
function
Pin
PD2
PD3
PD4
PD5
MISO
MOSI
SCK
SS
7.3 Functional description
The central element in the SPI system is the block containing the shift
register and the read data buffer (see Figure 7-1). The system is single
buffered in the transmit direction and double buffered in the receive
direction. This means that new data for transmission cannot be written
to the shifter until the previous transfer is complete; however, received
data is transferred into a parallel read data buffer so the shifter is free to
accept a second serial character. As long as the first character is read
out of the read data buffer before the next serial character is ready to be
transferred, no overrun condition occurs. A single MCU register address
is used for reading data from the read data buffer and for writing data to
the shifter.
The SPI status block represents the SPI status functions (transfer
complete, write collision, and mode fault) performed by the serial
peripheral status register (SPSR). The SPI control block represents
those functions that control the SPI system through the serial peripheral
control register (SPCR).
7.4 SPI transfer formats
During an SPI transfer, data is simultaneously transmitted and received.
A serial clock line synchronizes shifting and sampling of the information
on the two serial data lines. A slave select line allows individual selection
of a slave SPI device; slave devices that are not selected do not interfere
with SPI bus activities. On a master SPI device, the select line can
Technical Data
MC68HC11P2 — Rev 1.0
Serial Peripheral Interface (SPI)
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