Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI transfer formats
optionally be used to indicate a multiple master bus contention. Refer to
Figure 7-2.
MISO
PD2
S
M
M
S
MOSI
PD3
MCU
system clock
8-bit shift register
Read data buffer
Divider
÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128
Shift control logic
Pin
control
logic
SPI clock (master)
Select
S
Clock
logic
SCK
PD4
M
SS
PD5
OPT2 – Options register 2
MSTR
SPE
SPI control
SPIE
SPSR – SPI status register
SPCR – SPI control register
SPDR – SPI data register
SPI interrupt
request
Internal bus
Figure 7-1. SPI block diagram
MC68HC11P2 — Rev 1.0
Technical Data
Serial Peripheral Interface (SPI)
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