Freescale Semiconductor, Inc.
Motorola Interconnect Bus (MI BUS)
6.10.6 S2SR2 — MI BUS2 status register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SCI/MI 2 status 2 (S2SR2)
$0055 RAF2 0000 0000
0
0
0
0
0
0
0
RAF — Receiver active flag (read only)
1 = A character is being received.
0 = A character is not being received.
6.10.7 S2DRL — MI BUS2 data register
State
on reset
$0057 R7T7B R6T6B R5T5B R4T4B R3T3B R2T2B R1T1B R0T0B undefined
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SCI/MI 2 data low (S2DRL)
0
1
0
1
S1
D3
S2
D2
S3
D1
1
Pull field
A2
A1
A0
D4
D0 Push field
This register forms the 8-bit data/address word for the MI push field and
contains the 3-bit data word received as the MI pull field.
R/T[7:0] — Receiver/transmitter data bits [7:0]
READ: Reads access the three bits of pull field data (stored in bits
3–1) of the read-only MI BUS receive data register. Bits [7:4, 0] are a
fixed data pattern when a valid status and end-of-frame is returned. A
valid status is represented by the following data pattern: 0101 xxx1
(bits 7–0), where ‘xxx’ is the status. All ones in the receive data
register indicate that an error occurred on the MI BUS. Bits are
received LSB first by the MCU, and the status bits map as shown in
the above table.
WRITE: Writes access the eight bits of the write-only MI BUS transmit
data register. MI BUS devices require a 5-bit data pattern followed by
a 3-bit address pattern to be sent during the push field. The data
pattern is mapped to the lowest five bits of the data register and the
address to the highest three bits, as shown in the above table. Thus
MI-data[4:0] is written to S2DRL[4:0] and MI-address[2:0] is written to
S2DRL[7:5].
Technical Data
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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