Table 2-2 Signal and Package Information for the 144-Pin LQFP
State
Signal Name
RD
Pin No.
Type
During
Reset
Signal Description
45
Output
Tri-stated
Read Enable — RD is asserted during external memory read
cycles. When RD is asserted low, pins D0 - D15 become inputs
and an external device is enabled onto the data bus. When RD is
deasserted high, the external data is latched inside the device.
When RD is asserted, it qualifies the A0 - A16, PS, DS, and CSn
pins. RD can be connected directly to the OE pin of a static RAM or
ROM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), RD is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
WR
44
Output
Tri-stated
Write Enable — WR is asserted during external memory write
cycles. When WR is asserted low, pins D0 - D15 become outputs
and the device puts data on the bus. When WR is deasserted high,
the external data is latched inside the external device. When WR is
asserted, it qualifies the A0 - A16, PS, DS, and CSn pins. WR can
be connected directly to the WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), WR is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
PS
46
Output
Tri-stated
Program Memory Select — This signal is actually CS0 in the
EMI, which is programmed at reset for compatibility with the
56F80x PS signal. PS is asserted low for external program
memory access.
(CS0)
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), PS is tri-stated when the external bus is inactive.
CS0 resets to provide the PS function as defined on the 56F80x
devices.
(GPIOD8)
Input/
Input
Port D GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
To deactivate the Internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
56F8366 Technical Data, Rev. 2.0
24
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
