Signal Pins
Table 2-2 Signal and Package Information for the 144-Pin LQFP
State
Signal Name
A6
Pin No.
Type
During
Reset
Signal Description
17
Output
Tri-stated
Address Bus — A6 - A7 specify two of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A6–A7 and EMI control signals are tri-stated when the
external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOE2)
A7
Schmitt
Input/
Output
Input
Port E GPIO — These two GPIO pins can be individually
programmed as input or output pins.
18
19
After reset, the default state is Address Bus.
(GPIOE3)
To deactivate the internal pull-up resistor, set the appropriate
GPIO bit in the GPIOE_PUR register.
Example: GPIOE2, set bit 2 in the GPIOE_PUR register.
A8
Output
Tri-stated
Address Bus— A8 - A15 specify eight of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A8–A15 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOA0)
Schmitt
Input/
Output
Input
Port A GPIO — These eight GPIO pins can be individually
programmed as input or output pins.
A9
(GPIOA1)
20
21
22
23
24
25
26
After reset, the default state is Address Bus.
A10
(GPIOA2)
To deactivate the internal pull-up resistor, set the appropriate
GPIO bit in the GPIOA_PUR register.
A11
(GPIOA3)
Example: GPIOA0, set bit 0 in the GPIOA_PUR register.
A12
(GPIOA4)
A13
(GPIOA5)
A14
(GPIOA6)
A15
(GPIOA7)
56F8366 Technical Data, Rev. 2.0
Freescale Semiconductor
Preliminary
21
FREESCALE [ Freescale ]
