Table 2-2 Signal and Package Information for the 144-Pin LQFP
State
Signal Name
CLKO
Pin No.
Type
During
Reset
Signal Description
3
Output
Tri-Stated
Clock Output — This pin outputs a buffered clock signal. Using
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock and
postscaler clock. Other signals are also available for test purposes.
See Part 6.5.7 for details.
A0
138
Output
Tri-stated
Address Bus — A0 - A5 specify six of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A0–A5 and EMI control signals are tri-stated when the
external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOA8)
Input/
Input
Port A GPIO — These six GPIO pins can be individually
Output
programmed as input or output pins.
A1
(GPIOA9)
10
11
12
13
14
After reset, the default state is Address Bus.
A2
(GPIOA10)
To deactivate the internal pull-up resistor, set the appropriate
GPIO bit in the GPIOA_PUR register.
A3
(GPIOA11)
Example: GPIOA8, set bit 8 in the GPIOA_PUR register.
A4
(GPIOA12)
A5
(GPIOA13)
56F8366 Technical Data, Rev. 2.0
20
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
