Freescale Semiconductor, Inc.
Analog-to-Digital Converter
ATD Registers
PRS4, PRS3, PRS2, PRS1, PRS0 — Select Divide-By Factor for ATD
P-Clock Prescaler.
The binary value written to these bits (1 to 31) selects the divide-by
factor for the modulo counter-based prescaler. The P clock is divided
by this value plus one and then fed into a ÷2 circuit to generate the
ATD module clock. The divide-by-two circuit insures symmetry of the
output clock signal. Clearing these bits causes the prescale value
default to one which results in a ÷2 prescale factor. This signal is then
fed into the ÷2 logic. The reset state divides the P clock by a total of
four and is appropriate for nominal operation at 2 MHz. Table 16-3
shows the divide-by operation and the appropriate range of system
clock frequencies.
Table 16-3. Clock Prescaler Values
Prescale
Max P Clock(1)
Min P Clock(2)
Total Divisor
Value
00000
00001
00010
00011
00100
00101
00110
00111
01xxx
1xxxx
÷2
÷4
4 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
7 MHz
8 MHz
÷6
÷8
÷10
÷12
÷14
÷16
Do Not Use
1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value will become
maximum conversion rate that can be used on this ATD module.
2. Minimum conversion frequency is 500 kHz. Minimum P clock divisor value will become
minimum conversion rate that this ATD can perform.
MC68HC912DG128 — Rev 3.0
Technical Data
Analog-to-Digital Converter
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