Freescale Semiconductor, Inc.
Analog-to-Digital Converter
NOTE: Conversion of (VRH-VRL)/2 returns $7F, $80 or $81 in 8-bit mode.
Bit 7
SCF
0
6
0
0
5
0
0
4
0
0
3
0
0
2
CC2
0
1
CC1
0
Bit 0
CC0
0
RESET:
ATD0STAT0/ATD1STAT0 — ATD Status Register
$0066/$01E6
$0067/$01E7
ATD0STAT1/ATD1STAT1 — ATD Status Register
Bit 7
CCF7
0
6
CCF6
0
5
CCF5
0
4
CCF4
0
3
CCF3
0
2
CCF2
0
1
CCF1
0
Bit 0
CCF0
0
RESET:
The ATD status registers contain the flags indicating the completion of
ATD conversions.
Normally, it is read-only. In special mode, the SCF bit and the CCF bits
may also be written.
SCF — Sequence Complete Flag
This bit is set at the end of the conversion sequence when in the
single conversion sequence mode (SCAN = 0 in ATDxCTL5) and is
set at the end of the first conversion sequence when in the continuous
conversion mode (SCAN = 1 in ATDxCTL5). When AFFC = 0, SCF is
cleared when a write is performed to ATDxCTL5 to initiate a new
conversion sequence. When AFFC = 1, SCF is cleared after the first
result register is read.
CC[2:0] — Conversion Counter for Current Sequence of Four or Eight
Conversions
This 3-bit value reflects the contents of the conversion counter pointer
in a four or eight count sequence. This value also reflects which result
register will be written next, indicating which channel is currently being
converted.
CCF[7:0] — Conversion Complete Flags
Technical Data
MC68HC912DG128 — Rev 3.0
Analog-to-Digital Converter
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