Freescale Semiconductor, Inc.
Analog-to-Digital Converter
ATD Registers
When the AWAI bit is set and the module enters wait mode, most of
the clocks stop and the analog portion powers down. When the
module comes out of wait, it is recommended that a stabilisation delay
(stop and ATD power up recovery time, tSR) is allowed before new
conversions are started. Additionally, the ATD does not re-initialise
automatically on leaving wait mode.
ASCIE — ATD Sequence Complete Interrupt Enable
0 = Disables ATD interrupt
1 = Enables ATD interrupt on sequence complete
ASCIF — ATD Sequence Complete Interrupt Flag
Cannot be written in any mode.
0 = No ATD interrupt occurred
1 = ATD sequence complete
Bit 7
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
FRZ1
0
Bit 0
FRZ0
0
0
0
RESET:
ATD0CTL3/ATD1CTL3 — ATD Control Register 3
$0063/$01E3
FRZ1, FRZ0 — Background Debug (Freeze) Enable (suspend module
operation at breakpoint)
When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint is encountered. These two bits
determine how the ATD will respond when background debug mode
becomes active.
Table 16-1. ATD Response to Background Debug Enable
FRZ1
FRZ0
ATD Response
Continue conversions in active background mode
Reserved
0
0
1
1
0
1
0
1
Finish current conversion, then freeze
Freeze when BDM is active
MC68HC912DG128 — Rev 3.0
Technical Data
Analog-to-Digital Converter
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