Freescale Semiconductor, Inc.
Analog-to-Digital Converter
ATD Registers
Each of these bits are associated with an individual ATD result
register. For each register, this bit is set at the end of conversion for
the associated ATD channel and remains set until that ATD result
register is read. It is cleared at that time if AFFC bit is set, regardless
of whether a status register read has been performed (i.e., a status
register read is not a pre-qualifier for the clearing mechanism when
AFFC = 1). Otherwise the status register must be read to clear the
flag.
Bit 7
SAR9
0
6
SAR8
0
5
SAR7
0
4
SAR6
0
3
SAR5
0
2
SAR4
0
1
SAR3
0
Bit 0
SAR2
0
RESET:
ATD0TESTH/ATD1TESTH — ATD Test Register
$0068/$01E8
Bit 7
SAR1
0
6
SAR0
0
5
RST
0
4
TSTOUT
0
3
TST3
0
2
TST2
0
1
TST1
0
Bit 0
TST0
0
RESET:
ATD0TESTL/ATD1TESTL — ATD Test Register
$0069/$01E9
The test registers control various special modes which are used
during manufacturing. The test register can be read or written only in
the special modes. In the normal modes, reads of the test register
return zero and writes have no effect.
SAR[9:0] — SAR Data
Reads of this byte return the current value in the SAR. Writes to this
byte change the SAR to the value written. Bits SAR[9:0] reflect the ten
SAR bits used during the resolution process for a 10-bit result.
MC68HC912DG128 — Rev 3.0
Technical Data
Analog-to-Digital Converter
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