Freescale Semiconductor, Inc.
Analog-to-Digital Converter
V
RHx
RC DAC ARRAY
AND COMPARATOR
REFERENCE
SUPPLY
V
RLx
V
DDA
V
SSA
S
SAR
L
ANx7/PADx7
ANx6/PADx6
ANx5/PADx5
ANx4/PADx4
ANx3/PADx3
ANx2/PADx2
ANx1/PADx1
ANx0/PADx0
R
N
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
C
ANALOG MUX
AND
N
M
I
SAMPLE BUFFER AMP
D
A
PORT AD
DATA INPUT REGISTER
CLOCK
SELECT/PRESCALE
INTERNAL BUS
Figure 16-1. Analog-to-Digital Converter Block Diagram
16.3 Functional Description
A single conversion sequence consists of four or eight conversions,
depending on the state of the select 8 channel mode (S8CM) bit when
ATDxCTL5 is written. There are eight basic conversion modes. In the
non-scan modes, the SCF bit is set after the sequence of four or eight
conversions has been performed and the ATD module halts. In the scan
modes, the SCF bit is set after the first sequence of four or eight
conversions has been performed, and the ATD module continues to
restart the sequence. In both modes, the CCF bit associated with each
register is set when that register is loaded with the appropriate
conversion result. That flag is cleared automatically when that result
register is read. The conversions are started by writing to the control
registers.
Technical Data
MC68HC912DG128 — Rev 3.0
Analog-to-Digital Converter
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