Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Registers
in PBCTL, $B0) the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in
PBFLG ($B1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
BIT 7
MCZI
0
6
MODMC
0
5
RDMCL
0
4
ICLAT
0
3
FLMC
0
2
MCEN
0
1
MCPR1
0
BIT 0
MCPR0
0
RESET:
MCCTL — 16-Bit Modulus Down-Counter Control Register
$00A6
Read: any time
Write: any time
MCZI — Modulus Counter Underflow Interrupt Enable
0 = Modulus counter interrupt is disabled.
1 = Modulus counter interrupt is enabled.
MODMC — Modulus Mode Enable
0 = The counter counts once from the value written to it and will
stop at $0000.
1 = Modulus mode is enabled. When the counter reaches $0000,
the counter is loaded with the latest value written to the
modulus count register.
NOTE: For proper operation, the MCEN bit should be cleared before modifying
the MODMC bit in order to reset the modulus counter to $FF.
RDMCL — Read Modulus Down-Counter Load
0 = Reads of the modulus count register will return the present
value of the count register.
1 = Reads of the modulus count register will return the contents of
the load register.
MC68HC912DG128 — Rev 3.0
Technical Data
Enhanced Capture Timer
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