Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Registers
BIT 7
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
DLY1
0
BIT 0
DLY0
0
0
0
RESET:
DLYCT — Delay Counter Control Register
$00A9
Read: any time
Write: any time
If enabled, after detection of a valid edge on input capture pin, the delay
counter counts the pre-selected number of M clock (module clock)
cycles, then it will generate a pulse on its output. The pulse is generated
only if the level of input signal, after the preset delay, is the opposite of
the level before the transition.This will avoid reaction to narrow input
pulses.
After counting, the counter will be cleared automatically.
Delay between two active edges of the input signal period should be
longer than the selected counter delay.
DLYx — Delay Counter Select
DLY1
DLY0
Delay
0
0
1
1
0
1
0
1
Disabled (bypassed)
256 M clock cycles
512 M clock cycles
1024 M clock cycles
MC68HC912DG128 — Rev 3.0
Technical Data
Enhanced Capture Timer
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