Freescale Semiconductor, Inc.
Enhanced Capture Timer
PAMOD — Pulse Accumulator Mode
0 = event counter mode
1 = gated time accumulation mode
PEDGE — Pulse Accumulator Edge Control
For PAMOD bit = 0 (event counter mode).
0 = falling edges on PT7 pin cause the count to be incremented
1 = rising edges on PT7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
0 = PT7 input pin high enables M divided by 64 clock to Pulse
Accumulator and the trailing falling edge on PT7 sets the PAIF
flag.
1 = PT7 input pin low enables M divided by 64 clock to Pulse
Accumulator and the trailing rising edge on PT7 sets the PAIF
flag.
PAMOD
PEDGE
Pin Action
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Div. by 64 clock enabled with pin high level
Div. by 64 clock enabled with pin low level
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
since the E÷64 clock is generated by the timer prescaler.
CLK1, CLK0 — Clock Select Bits
CLK1
CLK0
Clock Source
0
0
1
0
1
0
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock
frequency
1
1
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock
from the timer is always used as an input clock to the timer counter.
The change from one selected clock to the other happens
immediately after these bits are written.
Technical Data
MC68HC912DG128 — Rev 3.0
Enhanced Capture Timer
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