Freescale Semiconductor, Inc.
Enhanced Capture Timer
POLF3 – POLF0 — First Input Capture Polarity Status
These are read only bits. Write to these bits has no effect.
Each status bit gives the polarity of the first edge which has caused
an input capture to occur after capture latch has been read.
Each POLFx corresponds to a timer PORTx input.
0 = The first input capture has been caused by a falling edge.
1 = The first input capture has been caused by a rising edge.
BIT 7
6
0
0
5
0
0
4
0
0
3
PA3EN
0
2
PA2EN
0
1
PA1EN
0
BIT 0
PA0EN
0
0
0
RESET:
ICPACR — Input Control Pulse Accumulators Control Register
$00A8
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if
PAEN in PATCL ($A0) is cleared. If PAEN is set, PA3EN and PA2EN
have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if
PBEN in PBTCL ($B0) is cleared. If PBEN is set, PA1EN and PA0EN
have no effect.
Read: any time
Write: any time
PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable
0 = 8-Bit Pulse Accumulator is disabled.
1 = 8-Bit Pulse Accumulator is enabled.
Technical Data
MC68HC912DG128 — Rev 3.0
Enhanced Capture Timer
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
