Freescale Semiconductor, Inc.
Enhanced Capture Timer
Bit 7
C7F
0
6
C6F
0
5
C5F
0
4
C4F
0
3
C3F
0
2
C2F
0
1
C1F
0
Bit 0
C0F
0
RESET:
TFLG1 — Main Timer Interrupt Flag 1
$008E
TFLG1 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, write a one to the bit.
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with the
use of the ICOVW register ($AA) allows a timer interrupt to be generated
after capturing two values in the capture and holding registers instead of
generating an interrupt for every capture.
Read anytime. Write used in the clearing mechanism (set bits cause
corresponding bits to be cleared). Writing a zero will not affect current
status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or
a write into an output compare channel ($90–$9F) will cause the
corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel “n” Flag.
Bit 7
TOF
0
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
Bit 0
0
0
RESET:
TFLG2 — Main Timer Interrupt Flag 2
$008F
TFLG2 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, set the bit to one.
Read anytime. Write used in clearing mechanism (set bits cause
corresponding bits to be cleared).
Technical Data
MC68HC912DG128 — Rev 3.0
Enhanced Capture Timer
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