Freescale Semiconductor, Inc.
Enhanced Capture Timer
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC4 — Timer Input Capture/Output Compare Register 4
$0098–$0099
$009A–$009B
$009C–$009D
$009E–$009F
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC5 — Timer Input Capture/Output Compare Register 5
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC6 — Timer Input Capture/Output Compare Register 6
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC7 — Timer Input Capture/Output Compare Register 7
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when
a defined transition is sensed by the corresponding input capture
edge detector or to trigger an output action for output compare.
Technical Data
MC68HC912DG128 — Rev 3.0
Enhanced Capture Timer
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