欢迎访问ic37.com |
会员登录 免费注册
发布采购

68HC912DG128PV8 参数 Datasheet PDF下载

68HC912DG128PV8图片预览
型号: 68HC912DG128PV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
 浏览型号68HC912DG128PV8的Datasheet PDF文件第223页浏览型号68HC912DG128PV8的Datasheet PDF文件第224页浏览型号68HC912DG128PV8的Datasheet PDF文件第225页浏览型号68HC912DG128PV8的Datasheet PDF文件第226页浏览型号68HC912DG128PV8的Datasheet PDF文件第228页浏览型号68HC912DG128PV8的Datasheet PDF文件第229页浏览型号68HC912DG128PV8的Datasheet PDF文件第230页浏览型号68HC912DG128PV8的Datasheet PDF文件第231页  
Freescale Semiconductor, Inc.  
Enhanced Capture Timer  
Timer Registers  
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR  
register is set.  
TOF — Timer Overflow Flag  
Set when 16-bit free-running timer overflows from $FFFF to $0000.  
This bit is cleared automatically by a write to the TFLG2 register with  
bit 7 set. (See also TCRE control bit explanation.)  
Bit 7  
Bit 15  
Bit 7  
6
14  
6
5
13  
5
4
12  
4
3
11  
3
2
10  
2
1
9
1
Bit 0  
Bit 8  
Bit 0  
TC0 — Timer Input Capture/Output Compare Register 0  
$0090–$0091  
$0092–$0093  
$0094–$0095  
Bit 7  
Bit 15  
Bit 7  
6
14  
6
5
13  
5
4
12  
4
3
11  
3
2
10  
2
1
9
1
Bit 0  
Bit 8  
Bit 0  
TC1 — Timer Input Capture/Output Compare Register 1  
Bit 7  
Bit 15  
Bit 7  
6
14  
6
5
13  
5
4
12  
4
3
11  
3
2
10  
2
1
9
1
Bit 0  
Bit 8  
Bit 0  
TC2 — Timer Input Capture/Output Compare Register 2  
Bit 7  
Bit 15  
Bit 7  
6
14  
6
5
13  
5
4
12  
4
3
11  
3
2
10  
2
1
9
1
Bit 0  
Bit 8  
Bit 0  
TC3 — Timer Input Capture/Output Compare Register 3  
$0096–$0097  
MC68HC912DG128 — Rev 3.0  
Technical Data  
Enhanced Capture Timer  
For More Information On This Product,  
Go to: www.freescale.com  
 复制成功!