Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
15.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next clock. Writing to the high byte (TMODH) inhibits
the TOF bit and overflow interrupts until the low byte (TMODL) is written.
Reset sets the TIM counter modulo registers.
Register Name and Address: TMODH—$0023
Bit 7
Bit 15
1
6
14
1
5
13
1
4
12
1
3
11
1
2
10
1
1
9
1
Bit 0
Bit 8
1
Read:
Write:
Reset:
Register Name and Address: TMODL—$0024
Bit 7
Bit 7
1
6
6
1
5
5
1
4
4
1
3
3
1
2
2
1
1
1
1
Bit 0
Bit 0
1
Read:
Write:
Reset:
Figure 15-6. TIM Counter Modulo Registers (TMODH and TMODL)
NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
15.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers (TSC0 and TSC1):
•
•
•
•
•
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input
capture trigger
•
•
•
Selects output toggling on TIM overflow
Selects 100 percent PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Advance Information
214
MC68HC908RFRK2
Timer Interface Module (TIM)
MOTOROLA
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