Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0 and TIM channel 1 status and
control registers.
Setting MS0B disables the TIM channel 1 status and control register.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation.
See Table 15-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCH0 pin. See Table 15-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel 0 is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port B, and pin PTB0/TCH0 is available as a general-purpose I/O
pin. Table 15-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
NOTE: TIM channel 1 does not have an external pin associated with it.
Advance Information
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MC68HC908RFRK2
MOTOROLA
Timer Interface Module (TIM)
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