Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
I/O Registers
15.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers
NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Register Name and Address: TCNTH—$0021
Bit 7
Read: Bit 15
Write:
6
5
4
3
2
1
9
Bit 0
Bit 8
14
13
12
11
10
0
0
0
0
0
0
0
0
Reset:
Register Name and Address: TCNTL—$0022
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-5. TIM Counter Registers (TCNTH and TCNTL)
MC68HC908RFRK2
MOTOROLA
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Timer Interface Module (TIM)
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