Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
I/O Registers
Table 15-3. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA
Mode
Configuration
Pin under port control;
initial output level high
X0
X1
00
00
Output preset
Pin under port control;
initial output level low
00
00
01
10
Capture on rising edge only
Capture on falling edge only
Input capture
Capture on rising or
falling edge
00
11
01
01
01
1X
1X
1X
01
10
11
01
10
11
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
Output
compare or
PWM
Buffered output
compare or
buffered PWM
NOTE: Before enabling a TIM channel register for input capture operation, make
sure that the PTB/TCH0 pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel 0 is an output compare channel, this read/write bit
controls the behavior of the channel 0 output when the TIM counter
overflows. When channel 0 is an input capture channel, TOV0 has no
effect. Reset clears the TOV0 bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE: The state of TOV1 has no effect since there is no pin.
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
Channel 1 should not be configured in input capture mode.
WARNING: The user must configure TIM channel 1 in a mode other than input
capture. It is recommended that this procedure be part of the
initilaization of the system after reset.
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
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Timer Interface Module (TIM)
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