Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Table 7-4. Port D I/O Functions
8
2
Access to DDRA
@ $0007
Accesses to Data
Register @ $0003
DDRA
I/O Pin Mode
Read/Write
DDRD5
Read
Write
0
1
Input, High Impedance
Output
I/O Pin
*
3
DDRD5
PD5/CKOUT PD5/CKOUT
4
*Does not affect input, but stored to data register
**PD7 is input-only
5
6
NOTE
To avoid generating a glitch on an I/O port pin, data should be written
to the I/O port data register before writing a logical one to the
corresponding data direction register.
7
8
9
10
11
12
13
14
A
16
17
18
19
20
INPUT/OUTPUT PORTS
MC68HC805P18
7-6
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