Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7.6 I/O Port Programming
8
2
Each pin on ports A through port D (except pin 7 of port D) may be programmed
as an input or an output under software control as shown in Table 7-1, Table 7-2,
Table 7-3, and Table 7-4. The direction of a pin is determined by the state of its
corresponding bit in the associated port data direction register (DDR). A pin is
configured as an output if its corresponding DDR bit is set to a logic one. A pin is
configured as an input if its corresponding DDR bit is cleared to a logic zero.
3
4
Table 7-1. Port A I/O Functions
5
Access to DDRA
@ $0004
Access to Data
Register @ $0000
DDRA
I/O Pin Mode
6
Read/Write
Read
I/O Pin
Write
*
0
1
Input, High Impedance
Output
DDRA0–DDRA7
DDRA0–DDRA7
7
PA0–PA7
PA0–PA7
8
*Does not affect input, but stored to data register
9
10
11
12
13
14
A
Table 7-2. Port B I/O Functions
Access to DDRA
@ $0005
Access to Data
Register @ $0001
DDRB
I/O Pin Mode
Read/Write
Read
I/O Pin
Write
*
0
1
Input, High Impedance
Output
DDRB5–DDRB7
DDRB5–DDRB7
PB5–PB7
PB5–PB7
*Does not affect input, but stored to data register
Table 7-3. Port C I/O Functions
16
17
18
19
20
Access to DDRA
@ $0006
Accesses to Data
Register @ $0002
DDRA
I/O Pin Mode
Read/Write
Read
I/O Pin
Write
*
0
1
Input, High Impedance
Output
DDRC0–DDRC7
DDRC0–DDRC7
PC0–PC7
PC0–PC7
*Does not affect input, but stored to data register
INPUT/OUTPUT PORTS
Rev. 1.0
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
