Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7.3 Port B
Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with the SIOP
8
2
communications subsystem. The port B data register is located at address $0001
and its data direction register (DDR) is located at address $0005. Reset does not
affect the data registers, but clears the DDRs, thereby setting all of the port pins to
input mode. Writing a logic one to a DDR bit sets the corresponding port pin to
output mode (see Figure 7-2).
3
4
Port B may be used for general I/O applications when the SIOP subsystem is
disabled. The SPE bit in register SPCR is used to enable/disable the SIOP
subsystem. When the SIOP subsystem is enabled, port B registers are still
accessible to software. Writing to either of the port B registers while a data transfer
is under way could corrupt the data. See SECTION 11 SERIAL INPUT/OUTPUT
PORT for a discussion of the SIOP subsystem.
5
6
7
READ $0005
8
WRITE $0005
DATA DIRECTION
REGISTER BIT
RESET
(RST)
WRITE $0001
READ $0001
9
I/O
PIN
DATA
REGISTER BIT
OUTPUT
10
11
12
13
14
A
INTERNAL HC05
DATA BUS
Figure 7-2. Port B I/O Circuitry
16
17
18
19
20
INPUT/OUTPUT PORTS
MC68HC805P18
7-2
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