Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7.5 Port D
Port D is a 2-bit port with one bidirectional pin (PD5/CKOUT) and one input-only
8
2
pin (PD7). Pin PD7 is shared with the 16-bit timer. PD5 can be replaced with a
buffered OSC2 clock output via MOR1. The port D data register is located at
address $0003 and its data direction register (DDR) is located at address $0007.
Reset does not affect the data registers, but clears the DDRs, thereby setting
PD5/CKOUT to input mode. Writing a one to DDR bit 5 sets PD5/CKOUT to output
mode (see Figure 7-4).
3
4
Port D may be used for general I/O applications regardless of the state of the 16-bit
timer. Since PD7 is an input-only line, its state can be read from the port D data
register at any time.
5
6
READ $0007
7
WRITE $0007
DATA DIRECTION
RESET
(RST)
REGISTER BIT
8
WRITE $0003
READ $0003
I/O
PIN
DATA
REGISTER BIT
OUTPUT
9
INTERNAL HC05
DATA BUS
10
11
12
13
14
A
Figure 7-4. Port D I/O Circuitry
16
17
18
19
20
INPUT/OUTPUT PORTS
MC68HC805P18
7-4
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