Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8.4 Mask Option Registers (MOR)
8
2
The MOR consists of two EEPROM bytes located at $3F00 and $3F01. The MOR
holds the 16 option bits for:
• The SIOP data format, interrupt sensitivity
• COP enable/disable
3
• SIOP clock rate
4
• LVR enable/disable
• Stop conversion to halt, pullup/interrupt enable on port A
• Clock output option to replace PD5
5
6
When in the erased state, the EEPROM cells will read as logic zeros. These
registers are refreshed every 256 µs during power-on reset and every 16 ms after
the part is out of reset (assuming fOSC = 4 MHz).
7
8
Bit 7
Read: CLKOUT
Write:
6
5
4
3
2
1
0
LVRE
SWAIT
SPR1
SPR0
LSBF
LEVIRQ COPEN
MOR1
$3F00
9
10
11
12
13
14
A
Reset:
Unaffected by reset
= Unimplemented
Figure 8-2. Mask Option Register 1
Bit 7
6
5
4
3
2
1
0
Read:
Write:
Reset:
PA7PU
PA6PU PA5PU PA4PU PA3PU PA2PU
PA1PU
PA0PU
MOR2
$3F01
Unaffected by reset
= Unimplemented
Figure 8-3. Mask Option Register 2
16
17
18
19
20
COPEN — COP enable/disable
COPEN may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = The COP is disabled (erased state).
1 = The COP is enabled.
EEPROM
MC68HC805P18
8-4
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