Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
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SECTION 7
INPUT/OUTPUT PORTS
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7.1 Introduction
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In user mode, 20 bidirectional input/output (I/O) lines are arranged as two 8-bit I/O
ports (ports A and C), one 3-bit I/O port (port B), and one 1-bit I/O port (port D).
These ports are programmable as either inputs or outputs under software control
of the data direction registers (DDRs). An input-only pin is associated with port D.
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7.2 Port A
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Port A is an 8-bit bidirectional port which can share its pins with the IRQ interrupt
system as shown in Figure 7-1. Each port A pin is controlled by the corresponding
bits in a data direction register and a data register. The port A data register is
located at address $0000. The port A data direction register (DDRA) is located at
address $0004. Reset clears the DDRA, thereby initializing port A as an input port.
The port A data register is unaffected by reset.
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A
V
DD
MOR 2
(PULLUP INHIBIT)
READ $0004
WRITE $0004
DATA DIRECTION
REGISTER BIT
WRITE $0000
READ $0000
I/O
PIN
DATA
REGISTER BIT
OUTPUT
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100 µA
PULLUP
INTERNAL HC05
DATA BUS
RESET
(RST)
TO IRQ INTERRUPT
SYSTEM
Figure 7-1. Port A I/O Circuitry
INPUT/OUTPUT PORTS
Rev. 1.0
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