Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
3.2.3 Condition Code Register (CCR)
8
2
The CCR is a 5-bit register in which four bits are used to indicate the results of the
instruction just executed, and the fifth bit indicates whether interrupts are masked.
These bits can be individually tested by a program, and specific actions can be
taken as a result of their state. Each bit is explained in the following paragraphs.
3
CCR
H
I
N
Z
C
4
Half Carry (H)
5
This bit is set during ADD and ADC operations to indicate that a carry occurred
between bits 3 and 4.
6
Interrupt (I)
7
When this bit is set, the timer and external interrupt are masked (disabled). If an
interrupt occurs while this bit is set, the interrupt is latched and processed as
soon as the interrupt bit is cleared.
8
Negative (N)
9
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was negative.
10
11
12
13
14
A
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was zero.
Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit
(ALU) occurred during the last arithmetic operation. This bit is also affected
during bit test and branch instructions and during shifts and rotates.
16
17
18
19
20
CENTRAL PROCESSING UNIT
Rev. 1.0
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
