GENERAL RELEASE SPECIFICATION
August 27, 1998
12.5.1 SM-Bus Address Register (SMADR)
BIT 7
SMAD7
0
BIT 6
SMAD6
0
BIT 5
SMAD5
0
BIT 4
SMAD4
0
BIT 3
SMAD3
0
BIT 2
SMAD2
0
BIT 1
SMAD1
0
BIT 0
U
SMADR
$0020
R
W
reset:
SMAD1-SMAD7 are the slave address bits of the SM-Bus module.
12.5.2 SM-Bus Frequency Divider Register (SMFDR)
BIT 7
BIT 6
BIT 5
BIT 4
FD4
0
BIT 3
FD3
0
BIT 2
FD2
0
BIT 1
FD1
0
BIT 0
FD0
0
SMFDR
$0021
R
W
reset:
U
U
U
FD0-FD4 are used for clock rate selection. The serial bit clock frequency is equal
to the CPU clock divided by the divider shown in Table 12-1.
For a 4MHz external crystal operation (2MHz internal operating frequency), the
serial bit clock frequency of the SM-Bus ranges from 460Hz to 90909Hz. After
POR the clock rate is set to 90909Hz.
Table 12-1. SM-Bus Clock Prescaler
FD4, FD3, FD2, FD1, FD0
DIVIDER
FD4,FD3, FD2, FD1, FD0
DIVIDER
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
22
24
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
352
384
28
448
34
544
44
704
48
768
56
896
68
1088
1408
1536
1792
2176
2816
3072
3584
4352
88
96
112
136
176
192
224
272
MOTOROLA
12-6
SM-BUS
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
