August 27, 1998
GENERAL RELEASE SPECIFICATION
SRW — Slave Read/Write Select
When SMAAS is set, the R/W command bit of the calling address sent from
master is latched into the R/W command bit (SRW). By checking this bit, the
CPU can select slave transmit/receive mode according to the command of
master.
1 = Read from slave, from calling master.
0 = Write to slave from calling master.
SMIF — SM-Bus Interrupt Flag
1 = An SM-Bus interrupt has occurred.
0 = An SM-Bus interrupt has not occurred.
This bit is set when one of the following events occur:
– Transmission (either transmit or receive mode) of one byte
completed. The bit is set at the falling edge of the 9th clock.
– Receive a calling address which matches its own specific address in
slave receive mode.
– Arbitration lost.
RXAK — Receive Acknowledge
When this bit is “0”, it indicates an acknowledge signal has been received after
the completion of 8 bits data transmission on the bus. If RXAK is “1”, it means
no acknowledge signal is detected at the 9th clock. This bit is set upon reset.
1 = No acknowledgment signal detected.
0 = Acknowledgment signal detected after 8 bits data transmitted.
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-9
FREESCALE [ Freescale ]
