August 27, 1998
GENERAL RELEASE SPECIFICATION
12.4.7 Clock Synchronization
Start counting high period
WAIT
SCL1
SCL2
SCL
Internal counter reset
Figure 12-3. Clock Synchronization
Since wired-AND logic is performed on SCL line, a high to low transition on the
SCL line will affect the devices connected to the bus. The devices start counting
their low period and once a device's clock has gone low, it will hold the SCL line
low until the clock high state is reached. However, the change of low to high in this
device clock may not change the state of the SCL line if another device clock is
still within its low period. Therefore the synchronized clock SCL will be held low by
the device with the longest low period. Devices with shorter low periods enter a
high wait state during this time (See Figure 12-2). When all devices concerned
have counted off their low period, the synchronized SCL line will be released and
go high. There will then be no difference between the device clocks and the state
of the SCL line and all devices will start counting their high periods. The first
device to complete its high period will again pull the SCL line low.
12.4.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data trans-
fer. Slave devices may hold the SCL low after completion of one byte. In such
cases the device will halt the bus clock and force the master clock into a wait state
until the slave releases the SCL line.
12.5 SM-BUS REGISTERS
There are five registers used in the SM-Bus interface. They are described in the
following paragraphs.
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-5
FREESCALE [ Freescale ]
