GENERAL RELEASE SPECIFICATION
August 27, 1998
12.5.5 SM-Bus Data I/O Register (SMDR)
BIT 7
SMD7
0
BIT 6
SMD6
0
BIT 5
SMD5
0
BIT 4
SMD4
0
BIT 3
SMD3
0
BIT 2
SMD2
0
BIT 1
SMD1
0
BIT 0
SMD0
0
SMDR
$0024
R
W
reset:
In master transmit mode, data written to this register is sent (MSB first) to the bus
automatically. In master receive mode, reading from this register initiates receiving
of the next byte of data. In slave mode, the same function is available after it is
addressed.
12.5.6 SM-Bus logic Level
Two choices of logic level is available for the SM-Bus: TTL or CMOS.
BIT 7
TSEN
0
BIT 6
LVRON
1
BIT 5
BIT 4
SCLK
0
BIT 3
CSSEL
0
BIT 2
TCSEL
0
BIT 1
BIT 0
MCR
R
0
COPON
0
ESVEN SMINLEV
$000B
W
reset:
0
0
Figure 12-4. Miscellaneous Control Register (MCR)
SMINLEV — SM-Bus Input Level Select
This read/write bit selects whether SM-Bus input level is TTL or CMOS. Reset
clears the SMINLEV bit.
1 = TTL input level is selected.
0 = CMOS input level is selected.
12.5.7 SCL as16-bit Timer Input Capture
The SCL signal can be routed to the 16-bit Timer Input Capture by setting the
TCSEL bit in the Miscellaneous Control Register.
TCSEL — 16-bit Timer Input Capture Source Select
This read/write bit selects the input capture source to the 16-bit Timer. Reset
clears TCSEL.
1 = SM-Bus SCL is routed to input capture of 16-bit Timer.
0 = CPF or external TCAP pin (depends on the state of ICEN bit in ACR,
$1D) is routed to 16-bit Timer.
See section Input Capture of 16-bit Timer for more details.
MOTOROLA
12-10
SM-BUS
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
