August 27, 1998
GENERAL RELEASE SPECIFICATION
MSB
1
LSB
MSB
1
LSB
SCL
SDA
1
0
0
0
0
1
1
1
0
0
0
0
1
1
Acknowledge bit
No acknowledge
START signal
STOP signal
MSB
LSB
1
MSB
1
LSB
1
SCL
1
1
0
0
0
0
1
1
0
0
0
0
1
Acknowledge bit
No acknowledge
SDA
START signal
STOP signal
repeated START signal
Figure 12-2. SM-Bus Transmission Signal Diagram
12.4.1 START Signal
When the bus is free, (i.e. no master device is engaging the bus and both SCL
and SDA lines are at logical high) a master may initiate communication by sending
a START signal. As shown in Figure 12-2, a START signal is defined as a high to
low transition of SDA while SCL is high. This signal denotes the beginning of new
data transfer (each data transfer may contain several bytes of data) and wakes up
all slaves.
12.4.2 Slave Address Transmission
The first byte of data transfer immediately after the START signal is the slave
address transmitted by the Master. This is a seven bit long calling address fol-
lowed by a R/W-bit. The R/W-bit tells the slave the desired direction of data trans-
fer.
Only the slave with a matched address will respond by sending back an acknowl-
edge bit by pulling SDA low on the 9th clock cycle. (See Figure 12-2)
12.4.3 Data Transfer
Once a successful slave addressing is achieved, the data transfer can proceed
byte by byte in the direction specified by the R/W- bit sent by the calling master.
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-3
FREESCALE [ Freescale ]
