August 27, 1998
GENERAL RELEASE SPECIFICATION
12.5.3 SM-Bus Control Register (SMCR)
BIT 7
SMEN
0
BIT 6
SMIEN
0
BIT 5
SMSTA
0
BIT 4
SMTX
0
BIT 3
TXAK
0
BIT 2
SMUX
0
BIT 1
U
BIT 0
U
SMCR
$0022
R
W
reset:
SMEN — SM-Bus Enable
If the SM-Bus enable bit (SMEN) is set, the SM-Bus interface system is
enabled. If SMEN is cleared, the interface is reset and disabled.
The SMEN bit must be set first before any bits of SMCR are set.
1 = SM-Bus enabled.
0 = SM-Bus disabled.
SMIEN — SM-Bus Interrupt Enable
If the SM-Bus interrupt enable bit (SMIEN) is set, the interrupt occurs provided
the SMIF flag in the status register is set and the I-bit in the Condition Code
Register is cleared. If SMIEN is cleared, the SM-Bus interrupt is disabled.
1 = SM-Bus interrupt enabled.
0 = SM-Bus interrupt disabled.
SMSTA — Master/Slave Select
Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START
signal is generated on the bus, and master mode is selected. When this bit is
changed from 1 to 0, a STOP signal is generated and the operating mode
changes from master to slave.
In master mode, a bit clear immediately followed by a bit set of this bit gener-
ates a repeated START signal (see Figure 12-2) without generating a STOP
signal.
1 = SM-Bus is set for master mode operation.
0 = SM-Bus is set for slave mode operation.
SMTX — Transmit/Receive Mode Select
This bit selects the SM-Bus to transmit or receive.
1 = SM-Bus is set for transmit mode.
0 = SM-Bus is set for receive mode.
TXAK — Acknowledge Enable
If the transmit acknowledge enable bit (TXAK) is cleared, an acknowledge sig-
nal will be sent out to the bus at the 9th clock bit after receiving one byte data.
When TXAK is set, no acknowledge signal response (i.e., acknowledge bit = 1).
1 = Do not send acknowledge signal.
0 = Send acknowledge signal at 9th clock bit.
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-7
FREESCALE [ Freescale ]
