GENERAL RELEASE SPECIFICATION
August 27, 1998
SMUX — SM-Bus Channel Select
The SMUX bit selects the channel for SM-Bus communications.
1 = Channel 1 (SDA1 and SCL1 pins) selected for SM-Bus.
0 = Channel 0 (SDA0 and SCL0 pins) selected for SM-Bus.
12.5.4 SM-Bus Status Register (SMSR)
BIT 7
BIT 6
BIT 5
BIT 4
SMAL
SMAL clr
0
BIT 3
0
BIT 2
SRW
BIT 1
SMIF
SMIF clr
0
BIT 0
SMSR
$0023
R
SMCF
SMAAS
SMBB
RXAK
W
reset:
1
0
0
0
1
SMCF — SM-Bus Data Transfer Complete
This bit indicates when a byte of data is being transmitted. When this bit is set,
the SMIF is also set. An interrupt request to the CPU is generated if the SMIEN
bit is also set.
1 = A byte transfer has been completed.
0 = A byte is being transferred.
SMAAS — SM-Bus Addressed as Slave
This bit is set when its own specific address (SMADR) matches the calling
address. When this bit is set, the SMIF is also set. An interrupt request to the
CPU is generated if the SMIEN bit is also set. Then CPU needs to check the
SRW bit and set its SMTX bit accordingly. Writing to the SM-Bus Control Regis-
ter clears this bit.
1 = Currently addressed as a slave.
0 = Not addressed.
SMBB — SM-Bus Busy
This bit indicates the status of the bus. When a START signal is detected, the
SMBB is set. If a STOP signal is detected, it is cleared.
1 = SM-Bus busy.
0 = SM-Bus idle.
SMAL — SM-Bus Arbitration Lost
This bit is set by hardware when the arbitration procedure is lost during a mas-
ter transmission. When this bit is set, the SMIF is also set. An interrupt request
to the CPU is generated if the SMIEN bit is also set. This bit must be cleared by
software.
1 = Lost arbitration in master mode.
0 = No arbitration lost.
MOTOROLA
12-8
SM-BUS
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
