GENERAL RELEASE SPECIFICATION
August 27, 1998
Internal bus
8
Control register
Status register
SMEN SMIEN SMSTA SMTX TXAK
SMCF SMAAS SMBB SMAL
SRW SMIF SRXAK
Frequency
divider
Address
register
register
M-Bus
interrupt
Interrupt
SCL
Address
comparator
M-Bus clock
generator
sync logic
SCL
control
TX shift
register
RX shift
register
START, STOP
detector and
arbitration
START, STOP
generator and
timing sync
TX
RX
control
control
SDA
control
SDA
Figure 12-1. SM-Bus Interface Block Diagram
12.3 SM-BUS SYSTEM CONFIGURATION
The SM-Bus system uses a serial data line (SDA) and a serial clock line (SCL) for
data transfer. All devices connected to it must have open drain or open collector
outputs and the logical “AND” function is performed on both lines by two pull up
resistors.
12.4 SM-BUS PROTOCOL
Normally a standard communication is composed of four parts, START signal,
Slave Address transmission, Data transfer, and STOP signal.These are described
briefly in the following sections and illustrated in Figure 12-2.
MOTOROLA
12-2
SM-BUS
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
