August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 12
SM-BUS
12.1 SM-BUS INTRODUCTION
The System Management Bus (SM-Bus) is a two wire, bidirectional serial bus
which provides a simple, efficient way for data exchange between devices.
This bus is suitable for applications which need frequent communications over a
short distance between a number of devices. It also provides a flexibility that
allows additional devices to be connected to the bus. The maximum data rate is
100kbit/s, and the maximum communication distance and number of devices that
can be connected is limited by a maximum bus capacitance of 400pF.
The SM-Bus is a true multi-master bus, including collision detection and arbitra-
tion to prevent data corruption if two or more masters intend to control the bus
simultaneously. This feature provides the capability for complex applications with
multi-processor control. It may also be used for rapid testing and alignment of end
products via external connections to an assembly-line computer.
Figure 12-1 shows a block diagram of the SM-Bus interface.
12.2 SM-BUS INTERFACE FEATURES
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Fully compatible to SM-Bus standard
Multi-master operation
Software programmable for one of 32 different serial clock frequencies
Software selectable acknowledge bit
Interrupt driven byte by byte data transfer
Arbitration lost driven interrupt with automatic mode switching from
master to slave
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Calling address identification interrupt
Generate/detect the START or STOP signal
Repeated START signal generation
Generate/recognize the acknowledge bit
Bus busy detection
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-1
FREESCALE [ Freescale ]
