GENERAL RELEASE SPECIFICATION
August 27, 1998
BIT 7
CHG
0
BIT 6
ATD2
0
BIT 5
ATD1
0
BIT 4
ICEN
0
BIT 3
CPIE
0
BIT 2
CPEN
0
BIT 1
0
BIT 0
ISEN
0
ACR
R
$001D
W
reset:
Figure 10-8. Analog Control Register (ACR)
Table 10-1. 16-bit Timer Input Capture Source
TCSEL ICEN
Selected TCAP Source
External TCAP via PB1
CPF from Analog Subsystem
SCL from SMBus
0
0
1
1
0
1
0
1
SCL from SMBus
When the input capture circuitry detects an active edge on the selected source, it
latches the contents of the free-running timer counter registers into the input cap-
ture registers as shown in Figure 10-6.
Latching values into the input capture registers at successive edges of the same
polarity measures the period of the selected input signal. Latching the counter val-
ues at successive edges of opposite polarity measures the pulse width of the sig-
nal.
The input capture registers are made up of two 8-bit read-only registers (ICRH,
ICRL) as shown in Figure 10-9. The input capture edge detector contains a
Schmitt trigger to improve noise immunity. The edge that triggers the counter
transfer is defined by the input edge bit (IEDG) in the TCR. Reset does not affect
the contents of the input capture registers.
The result obtained by an input capture will be one count higher than the value of
the free-running timer counter preceding the external transition. This delay is
required for internal synchronization. Resolution is affected by the prescaler,
allowing the free-running timer counter to increment once every four internal clock
cycles (eight oscillator clock cycles).
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICRH
R
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
$0014
W
reset:
U
ICRL7
U
U
ICRL6
U
U
ICRL5
U
U
ICRL4
U
U
ICRL3
U
U
ICRL2
U
U
ICRL1
U
U
ICRL0
U
ICRL
R
$0015
W
reset:
U = UNAFFECTED BY RESET
Figure 10-9. Input Capture Registers (ICRH, ICRL)
MOTOROLA
10-6
16-BIT TIMER
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
