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68HC705SB7 参数 Datasheet PDF下载

68HC705SB7图片预览
型号: 68HC705SB7
PDF下载: 下载PDF文件 查看货源
内容描述: 规格(通用版) [SPECIFICATION (General Release)]
分类和应用:
文件页数/大小: 170 页 / 1982 K
品牌: FREESCALE [ Freescale ]
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GENERAL RELEASE SPECIFICATION  
August 27, 1998  
10.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL)  
The functional block diagram of the 16-bit free-running timer counter and alternate  
counter registers is shown in Figure 10-4. The alternate counter registers behave  
the same as the timer registers, except that any reads of the alternate counter will  
not have any effect on the TOF flag bit and Timer interrupts. The alternate counter  
registers include a transparent buffer latch on the LSB of the 16-bit timer counter.  
INTERNAL  
DATA  
BUS  
READ  
ACRL  
LATCH  
ACRL ($001B)  
TMR LSB  
READ  
ACRH  
READ  
ACRH ($001A)  
($FFFC)  
INTERNAL  
CLOCK  
OSC  
RESET  
÷ 4  
16-BIT COUNTER  
(f  
÷ 2)  
Figure 10-4. Alternate Counter Block Diagram  
The alternate counter registers (ACRH, ACRL) shown in Figure 10-5 are read-  
only locations which contain the current high and low bytes of the 16-bit free-run-  
ning counter. Writing to the alternate counter registers has no effect. Reset of the  
device presets the timer counter to $FFFC.  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
ACRH  
$001A  
R
ACRH7  
ACRH6  
ACRH5  
ACRH4  
ACRH3  
ACRH2  
ACRH1  
ACRH0  
W
reset:  
1
ACRL7  
1
1
ACRL6  
1
1
ACRL5  
1
1
ACRL4  
1
1
ACRL3  
1
1
ACRL2  
1
1
ACRL1  
0
1
ACRL0  
0
ACRL  
$001B  
R
W
reset:  
Figure 10-5. Alternate Counter Registers (ACRH, ACRL)  
The ACRL latch is a transparent read of the LSB until the a read of the ACRH  
takes place. A read of the ACRH latches the LSB into the ACRL location until the  
ACRL is again read. The latched value remains fixed even if multiple reads of the  
ACRH take place before the next read of the ACRL. Therefore, when reading the  
MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to  
complete the read sequence.  
During power-on-reset (POR), the counter is initialized to $FFFC and begins  
counting after the oscillator start-up delay. Because the counter is sixteen bits and  
preceded by a fixed divide-by-four prescaler, the value in the counter repeats  
every 262,144 internal bus clock cycles (524,288 oscillator cycles).  
Reading the ACRH and ACRL in any order or any number of times does not have  
any effect on the 16-bit free-running counter or the TOF flag bit.  
MOTOROLA  
10-4  
16-BIT TIMER  
MC68HC05SB7  
REV 2.1