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68HC705SB7 参数 Datasheet PDF下载

68HC705SB7图片预览
型号: 68HC705SB7
PDF下载: 下载PDF文件 查看货源
内容描述: 规格(通用版) [SPECIFICATION (General Release)]
分类和应用:
文件页数/大小: 170 页 / 1982 K
品牌: FREESCALE [ Freescale ]
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August 27, 1998  
GENERAL RELEASE SPECIFICATION  
The timer registers (TMRH, TMRL) shown in Figure 10-3 are read-only locations  
which contain the current high and low bytes of the 16-bit free-running counter.  
Writing to the timer registers has no effect. Reset of the device presets the timer  
counter to $FFFC.  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
TMRH  
$0018  
R
TMRH7  
TMRH6  
TMRH5  
TMRH4  
TMRH3  
TMRH2  
TMRH1  
TMRH0  
W
reset:  
1
TMRL7  
1
1
TMRL6  
1
1
TMRL5  
1
1
TMRL4  
1
1
TMRL3  
1
1
TMRL2  
1
1
TMRL1  
0
1
TMRL0  
0
TMRL  
$0019  
R
W
reset:  
Figure 10-3. Programmable Timer Registers (TMRH, TMRL)  
The TMRL latch is a transparent read of the LSB until the a read of the TMRH  
takes place. A read of the TMRH latches the LSB into the TMRL location until the  
TMRL is again read. The latched value remains fixed even if multiple reads of the  
TMRH take place before the next read of the TMRL. Therefore, when reading the  
MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to  
complete the read sequence.  
During power-on-reset (POR), the counter is initialized to $FFFC and begins  
counting after the oscillator start-up delay. Because the counter is sixteen bits and  
preceded by a fixed divide-by-four prescaler, the value in the counter repeats  
every 262, 144 internal bus clock cycles (524, 288 oscillator cycles).  
When the free-running counter rolls over from $FFFF to $0000, the timer overflow  
flag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if  
the timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flag  
bit can only be reset by reading the TMRL after reading the TSR.  
Other than clearing any possible TOF flags, reading the TMRH and TMRL in any  
order or any number of times does not have any effect on the 16-bit free-running  
counter.  
NOTE  
To prevent interrupts from occurring between readings of the TMRH and TMRL,  
set the I bit in the condition code register (CCR) before reading TMRH and clear  
the I bit after reading TMRL.  
MC68HC05SB7  
REV 2.1  
16-BIT TIMER  
MOTOROLA  
10-3  
 
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