GENERAL RELEASE SPECIFICATION
August 27, 1998
The basis of the capture/compare Timer is a 16-bit free-running counter which
increases in count with each internal bus clock cycle.The counter is the timing ref-
erence for the input capture and output compare functions. The input capture and
output compare functions provide a means to latch the times at which external
events occur, to measure input waveforms, and to generate output waveforms and
timing delays. Software can read the value in the 16-bit free-running counter at
any time without affect the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input capture and
output compare functions are pairs of 8-bit registers. Each register pair contains
the high and low byte of that function. Generally, accessing the low byte of a spe-
cific timer function allows full control of that function; however, an access of the
high byte inhibits that specific timer function until the low byte is also accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-four pres-
caler, the counter rolls over every 262,144 internal clock cycles. Timer resolution
with a 4 MHz crystal oscillator is 2 microsecond/count.
The interrupt capability, the input capture edge, and the output compare state are
controlled by the timer control register (TCR) located at $0012 and the status of
the interrupt flags can be read from the timer status register (TSR) located at
$0013.
10.1 TIMER REGISTERS (TMRH,TMRL)
The functional block diagram of the 16-bit free-running timer counter and timer
registers is shown in Figure 10-2. The timer registers include a transparent buffer
latch on the LSB of the 16-bit timer counter.
READ
TMRL
LATCH
TMRL ($0019)
TMR LSB
READ
TMRH
READ
TMRH ($0018)
($FFFC)
INTERNAL
CLOCK
OSC
RESET
÷ 4
16-BIT COUNTER
(f
÷ 2)
OVERFLOW (TOF)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 10-2. Programmable Timer Block Diagram
MOTOROLA
10-2
16-BIT TIMER
MC68HC05SB7
REV 2.1