August 27, 1998
GENERAL RELEASE SPECIFICATION
10.5 TIMER CONTROL REGISTER (TCR)
The timer control register is shown in Figure 10-12 performs the following func-
tions:
•
•
•
•
•
Enables input capture interrupts.
Enables output compare interrupts.
Enables timer overflow interrupts.
Control the active edge polarity of the TCAP signal.
Controls the active level of the TCMP output.
Reset clears all the bits in the TCR with the exception of the IEDG bit which is
unaffected.
BIT 7
ICIE
0
BIT 6
OCIE
0
BIT 5
TOIE
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
IEDG
BIT 0
OLVL
0
TCR
R
$0012
W
reset:
0
0
0
Unaffected
Figure 10-12. Timer Control Register (TCR)
ICIE - INPUT CAPTURE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the PB1/
TCAP pin or from CPF flag bit of the analog subsystem voltage comparator.
Reset clears the ICIE bit.
1 = Input capture interrupts enabled.
0 = Input capture interrupts disabled.
OCIE - OUTPUT COMPARE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the TCMP
pin. Reset clears the OCIE bit.
1 = Output compare interrupts enabled.
0 = Output compare interrupts disabled.
TOIE - TIMER OVERFLOW INTERRUPT ENABLE
This read/write bit enables interrupts caused by a timer overflow. Reset clears
the TOIE bit.
1 = Timer overflow interrupts enabled.
0 = Timer overflow interrupts disabled.
IEDG - INPUT CAPTURE EDGE SELECT
The state of this read/write bit determines whether a positive or negative transi-
tion on the TCAP pin or the CPF flag bit of voltage comparator in the analog
subsystem triggers a transfer of the contents of the timer register to the input
capture register. Reset has no effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture.
0 = Negative edge (high to low transition) triggers input capture.
MC68HC05SB7
REV 2.1
16-BIT TIMER
MOTOROLA
10-9
FREESCALE [ Freescale ]
