August 27, 1998
GENERAL RELEASE SPECIFICATION
NOTE
To prevent interrupts from occurring between readings of the ACRH and ACRL,
set the I bit in the condition code register (CCR) before reading ACRH and clear
the I bit after reading ACRL.
10.3 INPUT CAPTURE REGISTERS
INTERNAL
DATA
BUS
READ
ICRH
PB1
TCAP
EDGE
SELECT
& DETECT
LOGIC
ICRH ($0014)
INPUT
SELECT
MUX
ICRL ($0015)
READ
ICRL
LATCH
INTERNAL
CLOCK
OSC
÷ 4
16-BIT COUNTER
INPUT CAPTURE (ICF)
SCL
OF
CPF
(f
÷ 2)
FLAG
SMBUS BIT
TIMER
INTERRUPT
REQUEST
TCSEL
(bit 2 of $0B)
ICEN
(bit 4 of $1D)
RESET
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 10-6. Timer Input Capture Block Diagram
The input capture function is a means to record the time at which an event occurs.
The source of the event can be selected from the following:
•
•
•
External input via the PB1 pin
CPF flag from the voltage comparator in the analog subsystem
SCL signal from the SMBUS
The input capture source is selected by the TCSEL and ICEN bits.
BIT 7
TSEN
0
BIT 6
LVRON
1
BIT 5
BIT 4
SCLK
0
BIT 3
CSSEL
0
BIT 2
TCSEL
0
BIT 1
BIT 0
MCR
R
0
COPON
0
ESVEN SMINLEV
$000B
W
reset:
0
0
Figure 10-7. Miscellaneous Control Register (MCR)
MC68HC05SB7
REV 2.1
16-BIT TIMER
MOTOROLA
10-5
FREESCALE [ Freescale ]
