GENERAL RELEASE SPECIFICATION
August 27, 1998
Software can use the output compare register to measure time periods, to gener-
ate timing delays, or to generate a pulse of specific duration or a pulse train of
specific frequency and duty cycle on the TCMP.
The planned action on the TCMP depends on the value stored in the OLVL bit in
the TCR, and it occurs when the value of the 16-bit free-running timer counter
matches the value in the output compare registers shown in Figure 10-3. These
registers are read/write bits and are unaffected by reset.
Writing to the OCRH before writing to the OCRL inhibits timer compares until the
OCRL is written. Reading or writing to the OCRL after reading the TSR will clear
the output compare flag bit (OCF). The output compare OLVL state will be clocked
to its output latch regardless of the state of the OCF.
BIT 7
OCRH7
U
BIT 6
OCRH6
U
BIT 5
OCRH5
U
BIT 4
OCRH4
U
BIT 3
OCRH3
U
BIT 2
OCRH2
U
BIT 1
OCRH1
U
BIT 0
OCRH0
U
OCRH
$0016
R
W
reset:
OCRL
$0017
R
OCRL7
U
OCRL6
U
OCRL5
U
OCRL4
U
OCRL3
U
OCRL2
U
OCRL1
U
OCRL0
U
W
reset:
U = UNAFFECTED BY RESET
Figure 10-11. Output Compare Registers (OCRH, OCRL)
To prevent OCF from being set between the time it is read and the time the output
compare registers are updated, use the following procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This also
clears the OCF flag bit in the TSR.
5. Enable interrupts by clearing the I bit in the condition code register.
A software example of this procedure is shown below.
9B
SEI
...
...
STA
LDA
STX
...
...
CLI
DISABLE INTERRUPTS
.....
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
.....
ENABLE INTERRUPTS
...
...
B7
B6
BF
...
...
9A
16
13
17
OCRH
TSR
OCRL
MOTOROLA
10-8
16-BIT TIMER
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
