Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8367 and 56F8167 are organized into functional groups, as detailed
in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals
present on a pin.
Table 2-1 Functional Group Pin Allocations
Number of Pins in Package
Functional Group
56F8367
56F8167
Power (VDD or VDDA
)
9
9
Power Option Control
1
7
1
7
Ground (VSS or VSSA
)
Supply Capacitors1 & VPP
6
6
PLL and Clock
4
24
16
10
6
4
24
16
10
6
Address Bus
Data Bus
Bus Control
Interrupt and Program Control
Pulse Width Modulator (PWM) Ports
Serial Peripheral Interface (SPI) Port 0
Serial Peripheral Interface (SPI) Port 1
26
4
13
4
—
4
4
Quadrature Decoder Port 02
Quadrature Decoder Port 13
4
4
4
—
4
Serial Communications Interface (SCI) Ports2
CAN Ports
2
21
6
—
21
2
Analog to Digital Converter (ADC) Ports
Timer Module Ports
JTAG/Enhanced On-Chip Emulation (EOnCE)
Temperature Sense
5
5
1
—
7
Dedicated GPIO
—
1. If the on-chip regulator is disabled, the V
pins serve as 2.5V V
power inputs
CAP
DD_CORE
2. Alternately, can function as Quad Timer pins
3. Pins in this section can function as Quad Timer, SPI #1, or GPIO
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
15
FREESCALE [ Freescale ]
