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56F8345 参数 Datasheet PDF下载

56F8345图片预览
型号: 56F8345
PDF下载: 下载PDF文件 查看货源
内容描述: 16位数字信号控制器 [16-bit Digital Signal Controllers]
分类和应用: 控制器
文件页数/大小: 164 页 / 2236 K
品牌: FREESCALE [ Freescale ]
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Table 2-2 Signal and Package Information for the 128-Pin LQFP  
State  
During  
Reset  
Signal  
Name  
Pin No.  
Type  
Signal Description  
CLKO  
6
Output  
In reset,  
output is  
disabled  
Clock Output — This pin outputs a buffered clock signal. Using  
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be  
programmed as any of the following: disabled, CLK_MSTR  
(system clock), IPBus clock, oscillator output, prescaler clock  
and postscaler clock. Other signals are also available for test  
purposes.  
See Part 6.5.7 for details.  
A8  
15  
Output  
In reset,  
output is  
disabled,  
pull-up is  
enabled  
Address Bus — A8 - A13 specify six of the address lines for  
external program or data memory accesses. Depending upon  
the state of the DRV bit in the EMI bus control register (BCR), A8  
- A13 and EMI control signals are tri-stated when the external  
bus is inactive.  
(GPIOA0)  
Schmitt  
Input/  
Output  
Port A GPIO — These six GPIO pins can be individually  
programmed as input or output pins.  
A9  
(GPIOA1)  
16  
17  
18  
19  
20  
27  
After reset, these pins default to address bus functionality and  
must be programmed as GPIO.  
A10  
(GPIOA2)  
To deactivate the internal pull-up resistor, clear the appropriate  
GPIO bit in the GPIOA_PUR register.  
A11  
(GPIOA3)  
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.  
A12  
(GPIOA4)  
Note: Primary function is not available in this package  
configuration; GPIO function must be used instead.  
A13  
(GPIOA5)  
GPIOB0  
Schmitt  
Input/  
Output  
Input,  
pull-up  
enabled  
Port B GPIO — These four GPIO pins can be individually  
programmed as an input or output pin.  
(A16)  
Output  
Address Bus — A16 - A19 specify four of the address lines for  
external program or data memory accesses. Depending upon  
the state of the DRV bit in the EMI bus control register (BCR),  
A16 - A19 and EMI control signals are tri-stated when the  
external bus is inactive.  
GPIOB1  
28  
29  
30  
(A17)  
GPIOB2  
After reset, the default state is GPIO.  
(A18)  
To deactivate the internal pull-up resistor, clear bit 0 in the  
GPIOB_PUR register.  
GPIOB3  
Example: GPIOB1, clear bit 1 in the GPIOB_PUR register.  
(A19)  
56F8345 Technical Data, Rev. 17  
22  
Freescale Semiconductor  
Preliminary  
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