Table 2-2 Signal and Package Information for the 128-Pin LQFP
State
During
Reset
Signal
Name
Pin No.
Type
Signal Description
TRST
114
Schmitt
Input
Input,
pulled high
internally
Test Reset — As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted whenever RESET is
asserted. The only exception occurs in a debugging environment
when a hardware device reset is required and the JTAG/EOnCE
module must not be reset. In this case, assert RESET, but do not
assert TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Note: For normal operation, connect TRST directly to VSS. If the
design is to be used in a debugging environment, TRST may be tied to
VSS through a 1K resistor.
PHASEA0
(TA0)
127
Schmitt
Input
Input,
pull-up
enabled
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Schmitt
Input/
Output
(GPIOC4)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed
as an input or output pin.
Output
After reset, the default state is PHASEA0.
To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.
PHASEB0
(TA1)
128
Schmitt
Input
Input,
pull-up
enabled
Phase B — Quadrature Decoder 0, PHASEB input
Schmitt
Input/
TA1 — Timer A, Channel 1
Output
(GPIOC5)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed
as an input or output pin.
Output
After reset, the default state is PHASEB0.
To deactivate the internal pull-up resistor, clear bit 5 of the
GPIOC_PUR register.
56F8345 Technical Data, Rev. 17
26
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
